Semiconductor device

ABSTRACT

A semiconductor device includes external interface terminals and processing circuits, and it is fed with an operating power source when detachably set in a host equipment. Power source feeding terminals (VCC, VSS) among the external interface terminals are long enough to keep touching the corresponding terminals of the host equipment for, at least, a predetermined time period since the separation of an extraction detecting terminal among the external interface terminals, from the corresponding terminal of the host equipment, and they are formed to be longer in the extraction direction of the semiconductor device than the extraction detecting terminal. These power source feeding terminals are a power source terminal and a ground terminal, and any power source compensating capacitor is not connected between the power source terminal and the ground terminal. Since a time period required till the cutoff of the power source can be easily ensured, a capacitor for compensating the operating power source at the power source cutoff which occurs midway of an operation is not necessitated.

FIELD OF THE INVENTION

The present invention relates to a semiconductor device such as a memorycard, or a card device represented by a multifunction card in which amicrocomputer for an IC card, or the like is mounted on a nonvolatilememory chip. More particularly, it relates to techniques which areeffective when applied for the elimination of any inconvenienceascribable to the cutoff of power source feed as occurs in a case wherethe semiconductor device is extracted from a host equipment during itsoperation.

BACKGROUND OF THE INVENTION

It is stated in Patent Document 1 that a detection terminal pulled downin a card device, and a terminal pulled up inside a card slot areemployed for detecting the setting and extraction of the card device inand from the card slot. When the card device has been set in the cardslot, the detection terminal touches the corresponding terminal of thecard slot and pulls the potential of the corresponding terminal insidethe card slot, to the ground. Upon detecting the ground potential, thecard slot side starts the feed of an operating power source to the carddevice. When the card device has been extracted, the detection terminalthereof is separated from the corresponding terminal of the card slot,whereby the, corresponding terminal is brought to a power sourcevoltage. Upon detecting the power source voltage, the card slot sidestops the feed of the power source to the extracted card device.

[Patent Document 1] JP-A-2000-99215 (FIG. 5)

SUMMARY OF THE INVENTION

Any inconvenience which is incurred on a card side by power sourcecutoff based on card extraction, is not considered in the prior-arttechnique. The inventor's study has revealed that, when the feed of anoperating power source has been cut off to interrupt an operation whiledata are being rewritten in a memory card in which a flash memory ismounted, the destruction of data, the unrecoverable deteriorations ofcharacteristics, etc. are apprehended to occur. By way of example, whenthe operating power source is cut off midway of an erase processpreceding a write process, nonvolatile memory cells in an overerasedstate are sometimes left behind. Here, the “overerased state” of thenonvolatile memory cells signifies a state where the memory cell havingcompleted, for example, an erase verify process has a threshold voltagelower than a threshold voltage distribution to-be-assumed. Even when anonselection level is applied to the selection terminal of thenonvolatile memory cell in the overerased state, a current flows to thechannel of the memory cell with this memory cell held in its ON state.When such a normally-ON nonvolatile memory cell exists, a malfunctionoccurs also in a read operation for the other memory cell which shares abit line with the normally-ON cell. To cope with the drawback, aprevious application (Japanese Patent Application No. 2003-89691) filedby the same assignee as in the present US application has provided atechnique which is comparatively easy of eliminating the inconvenienceascribable to the power source cutoff based on the extraction of thecard device. More specifically, in a card device which is fed with anoperating power source when set in a card slot (card socket), theinstruction of an end process within the card is given by detecting apotential change which appears in the detection terminal of the card asis separated from the predetermined terminal of the card slot, beforethe power source feed from the card slot side is cut off in theextraction of the card from the card slot, and the card is thuspermitted to perform the end process by itself before the power sourcefeed is completely cut off.

In the previous application, however, the viewpoint of ensuring a timeperiod required for the end process has not been satisfactorily studiedyet. The inventor took note of the relationship between the extractiondetecting terminal and power source feeding terminals. Further, theinventor studied the conjoint use of a capacitor which compensates thepower source feed for a certain time period after the power sourcecutoff. In the card device having a small size, it is also considered touse an electric double layer capacitor which is well suited to obtain acomparatively large capacitance with a comparatively small occupationarea. It has been revealed, however, that the electric double layercapacitor exhibits a comparatively large internal resistance and isdifficult to attain a current necessary for the process. After all, ithas been revealed the best that the necessary processing time period isensured by noting the relationship between the power source feedingterminals and the extraction detecting terminal.

An object of the invention is to provide a semiconductor device which iscomparatively easy of ensuring a processing time period for coping withpower source cutoff based on extraction from a host equipment, and whichcan contribute to the reduction of a size.

The above and other objects and novel features of the invention willbecome apparent from the description of this specification when read inconjunction with the accompanying drawings.

Typical aspects of the invention disclosed in the present applicationwill be briefly outlined below.

[1] A semiconductor device includes external interface terminals andprocessing circuits, and it is fed with an operating power source whendetachably set in a host equipment. The external interface terminalsinclude power source feeding terminals, an extraction detectingterminal, and other terminals. The power source feeding terminals arelong enough to keep touching the corresponding terminals of the hostequipment for, at least, a predetermined time period since theseparation of the extraction detecting terminal from the correspondingterminal of the host equipment, and they are formed to be longer in anextraction direction than the extraction detecting terminal. These powersource feeding terminals are a power source terminal and a groundterminal, and any power source compensating capacitor is not connectedbetween the power source terminal and the ground terminal.

When the power source feeding terminals are lengthened more than theextraction detecting terminal in the extraction direction in thismanner, a time period till the cutoff of the power source can be easilymade comparatively long. In order to prevent the arrangement of theconnector terminals of the host equipment side from being changed, thepower source feeding terminals should preferably be extended in adirection in which the semiconductor device is inserted into the hostequipment. However, the distance of the extension is liable to belimited, and the necessary processing time period cannot be sometimesensured. Besides, in order to ensure the necessary processing timeperiod without changing the length and shape of the power source feedingterminals on the semiconductor device side, substantially the sameeffect as in the case of enlarging the length of the power sourcefeeding terminals can be attained by forming each of the power sourcefeeding terminals so as to have two, front and rear touch points withthe corresponding connector terminal of the host equipment side.However, complicated improvements are necessitated for the constructionof the connector terminal of the host equipment side. According to theexpedient specified above, the time period required till the powersource cutoff is easily ensured, and the complicated improvements arenot required for the construction of the corresponding connectorterminals of the host equipment side. The touch of the power sourcefeeding terminals for the longer time period dispenses with thecapacitor for compensating the operating power source at the powersource cutoff which occurs midway of an operation. Accordingly, a spacefor mounting the power source compensating capacitor is not required. Itis unnecessary to daringly adopt an electric double layer capacitorwhich is inappropriate for deriving a comparatively large current,though which can really afford a comparatively large capacitance with asmall size.

In a practicable aspect of the invention, decoupling capacitors areconnected between the power source terminal and the ground terminal.Since a capacitance necessary for each of the decoupling capacitors issmall, no areal burden is imposed by mounting the decoupling capacitors.

In a further practicable aspect of the invention, the power sourcefeeding terminals are made longer than the extraction detectingterminal, also on a side opposite to the extraction direction, and alength which the power source feeding terminals protrude on the oppositeside to the extraction direction, beyond the extraction detectingterminal, is smaller than a length which the power source feedingterminals protrude in the extraction direction. This aspect is effectivein a case where the power source feeding terminals are to be made longereven slightly.

[2] A semiconductor device based on another viewpoint of the inventionincludes external interface terminals and processing circuits, and it isfed with an operating power source when detachably set in a hostequipment. The external interface terminals include power source feedingterminals, an extraction detecting terminal, and other terminals. Thepower source feeding terminals are long enough to touch thecorresponding terminals of the host equipment for, at least, 1.0millisecond since the separation of the extraction detecting terminalfrom the corresponding terminal of the host equipment, with respect toan extraction speed of 2.5 meters/second. The power source feedingterminals are a power source terminal and a ground terminal, and anypower source compensating capacitor is not connected between the powersource terminal and the ground terminal.

The inventor's study has revealed that the speed at which thesemiconductor device is extracted from the host equipment may besatisfactorily supposed to be 2.5 meters/second as the highest speed.This value has taken into consideration, a speed in the case where, in astate in which the semiconductor device has been further pushed into acard socket of push-push type against the elastic forces of springs, itis directly protruded out. On this occasion, a processing time periodrequired till the cutoff of the power source has been estimated to beone millisecond. There has been considered, for example, a voltageapplication processing time period which is required for shifting thethreshold voltage of an overerased nonvolatile memory cell into anormal-erase threshold voltage distribution. A touch length derived fromsuch a relationship is ensured, whereby the processing time periodrequired till the power source cutoff can be ensured. As in theforegoing, the touch of the power source feeding terminals for thelonger time period dispenses with the capacitor for compensating theoperating power source at the power source cutoff which occurs midway ofan operation. Accordingly, a space for mounting the power sourcecompensating capacitor is not required. It is unnecessary to daringlyadopt an electric double layer capacitor which is inappropriate forderiving a comparatively large current, though which can really afford acomparatively large capacitance with a small size.

In a practicable aspect of the invention, decoupling capacitors areconnected between the power source terminal and the ground terminal.Since a capacitance necessary for each of the decoupling capacitors issmall, no areal burden is imposed by mounting the decoupling capacitors.

In a further practicable aspect of the invention, the power sourcefeeding terminals are formed to be longer in the extraction directionthan the extraction detecting terminal. As in the foregoing, this aspectattains the advantages that a time period required till the cutoff ofthe power source is easily ensured, and that complicated improvementsare not required for the construction of the connector terminals of thehost equipment side.

In a further practicable aspect of the invention, the power sourcefeeding terminals are made longer than the extraction detectingterminal, also on a side opposite to the extraction direction, and alength which the power source feeding terminals protrude on the oppositeside to the extraction direction, beyond the extraction detectingterminal, is smaller than a length which the power source feedingterminals protrude in the extraction direction. This aspect is effectivein a case where the power source feeding terminals are to be made longereven slightly.

[3] A semiconductor device based on still another viewpoint of theinvention includes external interface terminals and processing circuits,and it is fed with an operating power source when detachably set in ahost equipment. The external interface terminals are arranged in tworows in a direction crossing the extraction direction of thesemiconductor device. They include power source feeding terminals, anextraction detecting terminal, and other terminals. The power sourcefeeding terminals are long so as to extend from the first row over tothe second row, the extraction detecting terminal is arranged at thefirst row, and the other terminals are arranged at the first and secondrows. The power source feeding terminals are a power source terminal anda ground terminal, and any power source compensating capacitor is notconnected between the power source terminal and the ground terminal.

Thus, in case of a semiconductor device which originally includes tworows of external interface terminals, a time period till the cutoff ofthe power source is easily made comparatively long by forming the powersource feeding terminals so as to extend from the first row over to thesecond row. Moreover, in the case where the semiconductor deviceincludes the two terminal rows, the connector terminals of the cardsocket of the host equipment are originally in, at least, two rows, sothat two of the connector terminals can stably touch the power sourcefeeding terminals, and the stabilization of the power source feed can beeasily coped with. As in the foregoing, the touch of the power sourcefeeding terminals for the longer time period dispenses with thecapacitor for compensating the operating power source at the powersource cutoff which occurs midway of an operation. Accordingly, a spacefor mounting the power source compensating capacitor is not required. Itis unnecessary to daringly adopt an electric double layer capacitorwhich is inappropriate for deriving a comparatively large current,though which can really afford a comparatively large capacitance with asmall size.

In a practicable aspect of the invention, decoupling capacitors areconnected between the power source terminal and the ground terminal.Since a capacitance necessary for each of the decoupling capacitors issmall, no areal burden is imposed by mounting the decoupling capacitors.

Advantages which are attained by typical aspects of the inventiondisclosed in the present application, are as briefly described below.

Since it becomes comparatively easy to ensure the processing time periodfor coping with the cutoff of the power source attributed to theextraction from the host equipment, a space for mounting a capacitorwhich compensates the operating power source at the power source cutoffmidway of an operation is dispensed with, and this can contribute to thereduction of the size of the semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic plan view showing a memory card according to anexample of the present invention;

FIG. 2 is a plan view showing an example of the connections between theexternal interface terminals of the memory card and the connectorterminals of a card slot, in a setting completion state;

FIG. 3 is a plan view showing another example of the connections betweenthe external interface terminals of the memory card and the connectorterminals of the card slot, in the setting completion state;

FIG. 4 is a plan view showing still another example of the connectionsbetween the external interface terminals of the memory card and theconnector terminals of the card slot, in the setting completion state;

FIG. 5 is a circuit diagram exemplifying a circuit arrangement forperforming insertion/extraction detection by voltage detection;

FIG. 6 is a circuit diagram exemplifying a circuit arrangement forperforming the insertion/extraction detection by current detection;

FIG. 7 is a plan view showing an example in which the external interfaceterminals are arranged in two rows;

FIG. 8 is a plan view showing another example in which the externalinterface terminals are arranged in two rows;

FIG. 9 is a schematic plan view exemplifying a jumpout suppressionmechanism for the memory card;

FIG. 10 is a plan view exemplifying the circuit component mountingsurface of the memory card;

FIG. 11 is a block diagram of a memory card having multifunctions,according to the second example of the invention;

FIG. 12 is a plan view exemplifying the array of the external interfaceterminals of the memory card in FIG. 11;

FIG. 13 is a plan view showing the array of external interface terminalsas differs from the array in FIG. 12 in the point that antenna terminalsare enlarged;

FIG. 14 is a plan view exemplifying the array of external interfaceterminals as differs from the array in FIG. 12 in the point that thefront and rear positions of antenna terminals and a second groundterminal are reversed;

FIG. 15 is a plan view exemplifying the array of external interfaceterminals as differs from the array in FIG. 13 in the point that thefront and rear positions of antenna terminals and a second groundterminal are reversed; and

FIG. 16 is a plan view exemplifying the array of external interfaceterminals as differs from the array in FIG. 12 in the point that asecond ground terminal is abolished, and that antenna terminals arelengthened correspondingly.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

<<Memory Card>>

Shown in FIG. 1 is a memory card according to an example of the presentinvention. The memory card 1 includes a card substrate 4 on which aninterface control circuit (CNT) 2 and a flash memory (FLASH) 3 aremounted. The mounting surface of the card substrate 4 is covered with acasing 5, and external interface terminals are constructed so as to beexposed to the surface of the card substrate 4 opposite to the mountingsurface. In the figure, wiring lines on the interface control circuit 2as well as the flash memory 3 and the card substrate 4 are schematicallyshown.

The external interface terminals shown in FIG. 1 include a groundterminal VSS, a power source terminal VCC, a second ground terminalVSS2, a serial clock input terminal SCLK, an insertion/extractiondetection terminal INS, a bus status terminal BS, and data terminalsDAT0-DAT3. The ground terminal VSS, power source terminal VCC, andsecond ground terminal VSS2 are connected to the interface controlcircuit 2 as well as the flash memory 3, and they are used for feedingan operating power source. The serial clock input terminal SCLK,insertion/extraction detection terminal INS, bus status terminal BS, anddata terminals DAT0-DAT3 are connected to the interface control circuit2. When the memory card 1 is detachably set in the card slot of a hostequipment not shown, the external interface terminals touch theconnector terminals of the card slot, thereby to establish electricalconnections with the host equipment. Thus, a power source is fed fromthe host equipment to the memory card 1 through the ground terminal VSS,power source terminal VCC and second ground terminal VSS2. When thememory card 1 is fed with the operating power source, it has itspower-ON reset. After the power-ON reset, the interface control circuit2 performs an interface control conforming to a predetermined interfaceprotocol, between this control circuit 2 and the host equipment, and itsubjects the flash memory 3 to a memory interface control for filememory access. By the way, in an operation mode which does not use thedata terminals DAT1-DAT3, the data terminal DAT0 functions as a serialdata input/output terminal (SDIO).

The flash memory 3 includes a memory mat in which a large number ofnonvolatile memory cells being electrically erasable and programmableare arranged in the shape of a matrix. Although not especiallyrestricted, each of the nonvolatile memory cells has a stacked gatestructure which includes a source (source line connection), a drain (bitline connection), a channel, and a floating gate and a control gate(word line connection) stacked on the channel in a manner to beinsulated from each other. By way of example, an erase process isperformed in such a way that a negative high voltage is applied to aword line so as to extract electrons from the floating gate into a wellregion, and a write process is performed in such a way that a positivehigh voltage is applied as a word line voltage so as to inject hotcarriers from the drain region into the floating gate. Later thresholdvoltages as viewed from the control gate differ between in the eraseprocess and the write process, and information is stored owing to thedifference. The drain electrode of the nonvolatile memory cell isconnected to a corresponding bit line, and the source electrode thereofto a corresponding source line. In a data read operation or verifyoperation, a selection level is bestowed through the word line on thecontrol gate of one of the nonvolatile memory cells sharing the bitline, and a nonselection level is bestowed through the word line on thecontrol gate of the other of the nonvolatile memory cells sharing thebit line, whereby the logical value of read data is determined inaccordance with cases where the threshold voltage of the nonvolatilememory cell endowed with the selection level is lower than the selectionlevel, and where it is higher. On this occasion, when even either of thenonvolatile memory cells sharing the bit line is a normally-ONnonvolatile memory cell, the normal read operation cannot be performed.The “normally-ON nonvolatile memory cell” is a nonvolatile memory cellwhose threshold voltage is lower than the nonselection level, that is, anonvolatile memory cell which is in an overerased state.

The interface control circuit 2 subjects the flash memory 3 to accesscontrols as a file memory compatible with a hard disk. By way ofexample, the interface control circuit 2 manages the addresses of theflash memory 3 in a manner to be accessible to the data area thereof insector units, and it performs the allocation control of substitutesectors for defective sectors. In accesses to the flash memory 3, theinterface control circuit 2 performs the access controls of the eraseprocess, write process and read process by using the physical addresses.

<<Power Source Feeding Terminals>>

Although not especially restricted, the external interface terminals areshaped by the etching of conductive patterns on the card substrate 4.The second ground terminal VSS2, serial clock input terminal SCLK,insertion/extraction detection terminal INS, bus status terminal BS, anddata terminals DAT0-DAT3 have equal sizes, respectively, and they arearrayed at equal intervals in a row. In FIG. 1, an A-direction is aninsertion direction in the case where the memory card 1 is set in thehost equipment. The ground terminal VSS and the power source terminalVCC are formed to be longer in a direction opposite to the insertiondirection A.

Exemplified in FIG. 2 is the relationship between the external interfaceterminals of the memory card 1 and the connector terminals of the cardslot. Numeral 11 designates the connector terminal corresponding to thepower source terminal VCC, and numeral 10 the connector terminalcorresponding to the ground terminal VSS. Numerals 12-14 designate theconnector terminals corresponding to the serial clock input terminalSCLK, data terminal DAT3 and insertion/extraction detection terminal INSwhich represent the other external interface terminals. The touch pointsof the respective connector terminals 10-14 with the external interfaceterminals become the distal end parts thereof. The touch points betweenthe power source feeding connector terminals 10, 11 and the power sourcefeeding terminals VCC, VSS are spaced a distance D in the oppositedirection to the insertion direction A, relative to the touch points ofthe connector terminals 12-14 corresponding to the other externalinterface terminals. In inserting the memory card 1, accordingly, thepower source feeding terminals VCC, VSS are respectively connected withthe corresponding connector terminals earlier than the other externalinterface terminals by a touching time period corresponding to thedistance D. In extracting the memory card 1, the power source feedingterminals VCC, VSS are respectively separated from the correspondingconnector terminals later than the other external interface terminals bythe touching time period corresponding to the distance D. That is tosay, the cutoff of the power source can be delayed by the touching timeperiod corresponding to the distance D, after the other externalinterface terminals have been separated from the connector terminals ofthe card socket.

When, as stated above, the ground terminal VSS and the power sourceterminal VCC are formed to be long in the opposite direction to theinsertion direction A, a time period till the cutoff of the power sourcecan be easily made comparatively long. In contrast, the ground terminalVSS and the power source terminal VCC should favorably be extended inthe insertion direction (A-direction) in order that the arrangement ofthe connector terminals on the side of the host equipment may remainunchanged. On this occasion, however, the distance of the extension issusceptible to limitation, and it is sometimes impossible to ensure anecessary processing time period. Besides, in order to cope with thedelay of the power source cutoff without changing the length and shapeof each of the power source feeding terminals of the memory card 1, eachof these terminals may have two, front and rear touch points with thecorresponding connector terminal 10 or 11 on the host equipment side,whereby substantially the same effect as in the case of lengthening eachpower source feeding terminal can be attained. On this occasion,however, the construction of each of the connector terminals 10 and 11on the host equipment side requires complicated improvements. After all,when the ground terminal VSS and the power source terminal VCC areformed to be long in the opposite direction to the insertion direction Aof the memory card 1, the time period required till the power sourcecutoff can be easily ensured, and the complicated improvements are notrequired for the construction of each of the connector terminals 10 and11 on the host equipment side.

Shown in FIG. 3 is another example of the external interface terminalsof the memory card 1 and the connector terminals of the card slot. Twoconnector terminals 10A, 10B corresponding to the ground terminal VSSare disposed with their distal ends shifted, while two connectorterminals 11A, 11B corresponding to the power source terminal VCC aresimilarly disposed with their distal ends shifted. The distal ends ofthe shorter connector terminals 10A, 11A are located at the samepositions as those of the distal ends of the other connector terminalsin the card insertion direction, and the distal ends of the longerconnector terminals 10B, 11B are spaced from those of the shorterconnector terminals 10A, 11A by the distance D in the card insertiondirection. Also in this case, in the same manner as in FIG. 2, ininserting the memory card 1, the power source feeding terminals VCC, VSSare respectively connected with the corresponding connector terminalsearlier than the other interface terminals by the touching time periodcorresponding to the distance D. In extracting the card 1, the powersource feeding terminals VCC, VSS are respectively separated from thecorresponding connector terminals later than the other interfaceterminals by the touching time period corresponding to the distance D.In particular, each of the power source and ground terminals is providedwith the two power source feeding points (the connection points betweeneach power source feeding terminal and the corresponding connectorterminal), so that the stability of the feed of the power source afterthe setting of the memory card 1 can be enhanced.

Shown in FIG. 4 is still another example of the external interfaceterminals of the memory card 1 and the connector terminals of the cardslot. It is the same as in FIG. 3 that two connector terminals 11C, 11Dcorresponding to the power source terminal VCC are disposed with theirdistal ends shifted, while two connector terminals 10C, 10Dcorresponding to the ground terminal VSS are similarly disposed withtheir distal ends shifted. However, the distal end of each of theshorter connector terminals 10C, 11C is spaced from the distal ends ofthe other connector terminals by the distance D in the card insertiondirection, and the distal end of each of the longer connector terminals10D, 11D is further spaced from the distal ends of the shorter connectorterminals 10C, 11C by a distance F in the card insertion direction.Thus, in inserting the memory card 1, the power source feeding terminalsVCC, VSS are respectively connected with the corresponding connectorterminals earlier than the other external interface terminals by atouching time period corresponding to a distance (D+F) . In extractingthe card 1, the power source feeding terminals VCC, VSS are respectivelyseparated from the corresponding connector terminals later than theother interface terminals by the touching time period corresponding tothe distance (D+F). That is to say, the cutoff of the power source canbe delayed by the touching time period corresponding to the distance(D+F), after the other interface terminals have been separated from theconnector terminals of the card socket. In a state where the setting ofthe memory card 1 in the card socket has been completed, each of thepower source and ground terminals VCC, VSS has only one feeding point ofthe power source, but the difference of the touching time periods can beenlarged in correspondence with the distance (D+F).

The time period difference can be attained in inserting/extracting thecard, by lengthening the power source feeding terminals 10, 11. Insetting the card, the power-ON reset of the memory card 1 is effectedearlier owing to the time period difference, and in extracting the card,an end process for ending a midway process is performed before the powersource cutoff since the detection of the insertion/extraction earlier bythe time period difference. The details of the end process will bedescribed later. Especially in the invention, the length of the powersource feeding terminals 10, 11 is determined in consideration of a timeperiod difference which is required for the end process. The inventor'sstudy has revealed that a speed at which the memory card 1 is extractedfrom the host equipment may be satisfactorily supposed to be 2.5meters/second as the highest speed. This value has taken intoconsideration a speed in the case where, in a state in which asemiconductor device has been further pushed into a card socket ofpush-push type against the elastic forces of springs, the semiconductordevice is directly protruded out. On this occasion, one millisecond hasbeen estimated as a processing time period which is required till thepower source cutoff. There has been considered, for example, a voltageapplication processing time period which is required for shifting thethreshold voltage of an overerased nonvolatile memory cell into anormal-erase threshold voltage distribution. A touch length derived fromsuch a relationship is ensured, whereby the processing time periodrequired till the power source cutoff can be ensured. More specifically,each of the power source feeding terminals has a length with which itcan touch the corresponding terminal of the host equipment for, atleast, 1.0 millisecond with respect to the extraction speed of 2.5meters/second, after the extraction detecting terminal INS has beenseparated from the corresponding terminal of the host equipment. By wayof example, assuming that the extraction speed is 2.5 meters/second andthat the processing time period required till the power source cutoff isone millisecond, the distance D in each of FIGS. 2 and 3 is set at 2.5millimeters, and the distance (D+F) in FIG. 4 is set at 2.5 millimeters.

Exemplified in FIG. 5 is a circuit arrangement for insertion/extractiondetection. The connector terminal 14 of the card slot as corresponds tothe insertion/extraction detection terminal INS is pulled up through aresistor 21 inside the host equipment 23. Inside the memory card 1, theinsertion/extraction detection terminal INS is connected to the groundterminals VSS, VSS2 through a resistor 22. In order to permit thedetection of the extraction from the card slot by the memory card 1itself, the input of an amplifier 20, for example, is connected to theinsertion/extraction detection terminal INS so as to decide theextraction by the output of the amplifier 20. The connector terminal 14is pulled up to a power source voltage vcc in a floating state. When thememory card 1 has been inserted to bring the insertion/extractiondetection terminal INS into touch with the connector terminal 14, thisconnector terminal 14 is brought to a low level which is determined bythe voltage division ratio between the resistors 21 and 22. The hostequipment 23 detects the low level, whereby the setting of the memorycard 1 is recognized. The amplifier 20 has a level intermediate betweenthe low level and a ground level vss, as its input threshold voltage.Accordingly, the amplifier 20 outputs the low level when its inputvoltage is lower than the input threshold voltage, and it outputs a highlevel when not. When the insertion/extraction detection terminal INS hasbeen separated from the connector terminal 14 by the extraction of thememory card 1, the input of the amplifier 20 falls into the groundvoltage vss of circuitry, and the interface control circuit 2 canrecognize the extraction of the memory card 1 owing to the outputinversion of the amplifier 20.

Exemplified in FIG. 6 is another circuit arrangement for theinsertion/extraction detection. The connector terminal of the card slotas corresponds to the insertion/extraction detection terminal INS ispulled up through a resistor 21 inside the host equipment, in the samemanner as in FIG. 5. Inside the memory card 1, the insertion/extractiondetection terminal INS is connected to the inverting input terminal (−)of a differential amplifier 24. The output terminal of the differentialamplifier 24 is feedback-connected to the inverting input terminal (−)through a resistor 25. The ground terminals VSS, VSS2 are connected tothe noninverting input terminal (+) of the differential amplifier 24.Letting “i” denote a current fed to the inverting input terminal (−),and “R” denote the resistance of the negative feedback resistor 25, theoutput voltage Vout of the negative feedback differential amplifier 24becomes Vout=−i●R. The presence or absence of the current i which is fedto the insertion/extraction detection terminal INS can be detected bythe negative feedback differential amplifier 24, whereby thetouch/separation between the connector terminal of the host equipmentand the insertion/extraction detection terminal INS of the memory card 1becomes detectable.

Shown in FIG. 7 is an example in which the external interface terminalsare arranged in two rows. Signs TML denote the external interfaceterminals of the second row. The external interface terminals TML areused as, for example, data terminals added in case of increasing thenumber of parallel data input/output bits, or interface terminals in thecase where an IC card microcomputer for security is mounted on thememory card 1. The external interface terminals of the first row are thesame as in FIG. 1.

Shown in FIG. 8 is another example in which the external interfaceterminals are arranged in two rows. The point of difference of thisexample from the example in FIG. 7 lies in the arrangement of the powersource feeding terminals of the first row. As understood by comparingFIG. 8 with FIG. 1 or 7, the power source feeding terminals VSS, VCC arearranged so as to shift a distance G in the card insertion direction.The reason therefor is that the intervening wiring space between thefirst and second rows becomes smaller disadvantageously due to theaddition of the external interface terminals TML of the second row, sothis space is intended to enlarge even slightly. Besides, as understoodby comparing FIG. 8 with FIG. 7, the power source feeding terminals VSS,VCC are thickened relative to the other external interface terminals. Inthis way, when each of the connector terminals corresponding to thepower source feeding terminals is to have the two contacts or touchpoints, the manufacture of the connector terminals can be facilitated.

Exemplified in FIG. 9 is a jumpout suppression mechanism for the memorycard 1. Notches 30-32 are formed in both the side surfaces of the memorycard 1. Leaf springs 33-35 which come into elastic touch with the sidesurfaces of the memory card 1 are supported in cantilever fashion insidethe card slot 23 of the host equipment. In a state (shown at (A)) wherethe memory card 1 has been completely set in the card slot 23, the leafsprings 34, 35 enter the respectively corresponding notches 31, 32,thereby to position the memory card 1. The leaf spring 33 exerts apressing force on the side surface of the memory card 1. The card slot23 has, for example, the construction of a so-called “push-pushconfiguration” which allows the card 1 to be set therein or detachedtherefrom by a push-in manipulation. More specifically, the springs arecompressed by the displacement of the memory card inserted against thepressing forces of the springs, so as to latch the memory card by togglelatches, and the memory card is thereafter pushed in slightly, wherebythe latch of the memory card by the toggle latches is released, and thememory card is urged in an ejection direction by the elastic forces ofthe springs. In a state (shown at (B)) immediately after the memory card1 has been pushed slightly in the insertion direction A in the set stateshown at (A) in FIG. 9, so as to exert urging forces of the ejectiondirection on the memory card 1, the three leaf springs 33-35 lie inelastic touch with the side surfaces of the memory card 1 and exertslide resistances on these side surfaces, so that the violet jumpout ofthe memory card 1 is suppressed. The suppression contributes to loweringthe highest speed of the extraction of the memory card 1 from the hostequipment. In a case where a comparatively long time is required as thetime period of the end process, the suppression functions to shorten thedistance D or (D+F).

<<End Process>>

The end process in the extraction of the memory card 1 will bedescribed. This end process is a process (also termed “write-upprocess”) which uniformalizes the threshold voltages of the nonvolatilememory cells midway of, for example, the erase and erase verifyprocesses, into a predetermined threshold voltage distribution. Here,the instruction of the write-up process for the flash memory 3 is givenby a reset signal (not shown). That is, the flash memory 3 performs thewrite-up process when the reset signal is asserted midway of the eraseand erase verify processes. Assuming by way of example that the eraseprocess is performed for the nonvolatile memory cells in word line unitsinside the flash memory 3, the write-up process is a process whichwrites information lightly into the nonvolatile memory cells beingsubjects for the erase process. The “light write” is a write process inwhich a write high-voltage application time period is shorter than inthe ordinary write process, and in which, among the memory cellsto-be-erased, ones exhibiting negative threshold voltages have theirthreshold voltages heightened to positive voltages. In a case where awrite voltage is applied to a word line in the erase process proceedingin word line units, a potential difference which is applied to a chargeaccumulation layer for accumulating charges becomes greater in thememory cell whose threshold voltage is the negative voltage, than in thememory cell whose threshold voltage is the positive voltage. Therefore,information is written earlier into the memory cell whose thresholdvoltage is the negative voltage. The write-up process is intended tobring into the positive voltage, the threshold voltages of the memorycells which are in the overerased state, especially whose thresholdvoltages are the negative voltages, so that the application time periodof the write voltage may be shorter than in the ordinary write process.Thus, even when the power source has been undesirably cut off midway ofthe write of data before the complete cutoff of the power source feed,the memory card 1 can perform the process by itself so that the memorycells in the overerased state may not remain. In order to shorten thetime period of the write-up process, the application voltage may beheightened within a possible range.

Another end process is a process which completes the storage ofinformation into a management area necessary for the recognition of astorage area. An FAT (file allocation table) or a sector management areain a file memory must be guaranteed to be readable upon the closure ofthe power source. The sector management area, for example, storestherein the correspondence between logical addresses (sector addresses)and memory addresses, the validities of sectors, substitute addressesfor defective sectors, and so forth. When the storage of informationinto the FAT or the sector management area concerning the sectorsto-be-rewritten has been completed as the end process, it is possible tosuppress a situation where the process is interrupted with the data ofsuch an area being incomplete, so that the recognition of the storagearea such as the sectors becomes impossible. Supposing by way of examplea case where the sector management area of the sectors to-be-erased isalso erased together with the sector erase, the recognition of thesectors is anticipated to become completely impossible, withoutperforming the end process. Also the instruction of the end process maybe given as a reset signal for the flash memory 3. When the eraseprocess or write process is proceeding at the assertion of the resetsignal, the end process may be performed for completing the storage ofthe information into the FAT or the sector management area.

Still another end process is a process which completes the midwaystorage of information after the initialization process of thresholdvoltages. By way of example, when the erase process or write process isproceeding at the assertion of a reset signal, the write process for asector midway of write is completed, and management information, whichindicates that the sector is valid, is set in the corresponding sectormanagement area. The write process instructed by the host side can becompleted after erase, so that a write retry or the like process neednot be performed upon the re-closure of the power source.

<<Capacitor-free>>

As described above, when the power source feeding terminals VCC, VSS arelengthened more than the extraction detecting terminal INS in theextraction direction, the time period till the power source cutoff iseasily made comparatively long. Accordingly, a power source compensatingcapacitor need not be mounted between the power source wiring lineconnected to the power source terminal VCC and the ground wiring lineconnected to the ground terminal VSS, in order to compensate theoperating power source in the case of the power source cutoff during themidway process. Consequently, a space for mounting the power sourcecompensating capacitor is not required. It is unnecessary to daringlyadopt an electric double layer capacitor which is inappropriate forderiving a comparatively large current, though which can really afford acomparatively large capacitance with a small size.

Shown in FIG. 10 is the circuit component mounting surface of the memorycard 1. The power source wiring line 36 and the ground wiring line 37are representatively shown as the wiring lines. As stated before, anypower source compensating capacitor is not connected between the powersource wiring line 36 and the ground wiring line 37. In this example,two decoupling capacitors 38 which have a chattering reduction functionare respectively connected between the power source wiring line 36 andthe ground wiring line 37. Since a capacitance necessary for each of thedecoupling capacitors 38 is small, no areal burden is imposed bymounting the decoupling capacitors 38.

<<Multifunction Memory Card>>

Exemplified in FIG. 11 is a block diagram of a memory card havingmultifunctions, according to the second example of the invention. Thememory card 41 shown in the figure offers the multifunctions, forexample, an information storage function, and a security function whichaccompanies encrypt/decrypt processes, a verify process, etc. Thesecurity function is utilized for, for example, payment by a credit cardand accounting in transport facilities.

The memory card 41 is such that, on a wiring substrate which is formedwith a plurality of external terminals, there are mounted a cardcontroller 42, a nonvolatile storage device, for example, flash memory43 which is electrically rewritable and which is connected to the cardcontroller 42 by internal buses 45, and an IC (integrated circuit) cardmicrocomputer (a microcomputer for an IC card) 44 which is a securitycontroller and which is connected to the card controller 42 by internalbuses 46. Although not especially restricted, the card controller 42,flash memory 43 and IC card microcomputer 44 are respectivelyconstructed of individual semiconductor integrated circuit chips.

The card controller 42 has the external interface functions of thememory card conforming to, for example, multimedia card standards, thememory interface function of accessing the flash memory as a file memoryin accordance with the specifications thereof, and the IC cardmicrocomputer interface function of interfacing with the IC cardmicrocomputer by using memory card commands, etc.

The flash memory 43 includes electrically erasable and programmablenonvolatile memory cells though they are not especially shown. Each ofthe nonvolatile memory cells has a so-called “stacked gate structure”which includes a floating gate, or a so-called “split gate structure”which is configured of a memory transistor portion and a selectiontransistor portion and which includes an ONO (oxide-nitride-oxide)gate-insulating film, though the structure is not especially shown. Thenonvolatile memory cell has its threshold voltage heightened whenelectrons are injected into the floating gate or the like, and it hasits threshold voltage lowered when the electrons are extracted from thefloating gate or the like. Thus, the nonvolatile memory cell storestherein information corresponding to the magnitude of the thresholdvoltage relative to a word line voltage for data read. Under thecontrols of the card controller 42, the flash memory 43 is permitted toread out information stored in the nonvolatile memory cells, to store(for example, write) information in (into) the nonvolatile memory cells,and to initialize (for example, erase) the stored information of thenonvolatile memory cells.

The IC card microcomputer 44 includes a CPU, and a nonvolatile memory inwhich the operation programs of the CPU, control information to beutilized for verification, etc. are retained, though they are notespecially shown. This IC card microcomputer 44 executes the verifyprocess, the encrypt/decrypt processes, etc. in accordance with theoperation programs. Adoptable as the IC card microcomputer 44 is onewhich performs contact interfacing or noncontact interfacing with theexterior by itself, or one which performs dual interfacing capable ofboth the contact interfacing and the noncontact interfacing. Here, theIC card microcomputer 44 of the noncontact interfacing type is adopted,and it executes, for example, data input/output, clock input and resetsignal input through high-frequency communications which employ anantenna connected to terminals LA, LB. In the case of operating innoncontact interfacing fashion, the IC card microcomputer 44 is fed withelectric power from the antenna connected to the antenna terminals (LA,LB).

The memory card 41 includes external terminals C1-C5, C6, C6A, C6B, andC7-C13 as external interface terminals. Here, an example capable ofinputting/outputting 8-bit parallel data is mentioned. The terminal C1is a data terminal DAT3, the terminals C7-C9 are data terminalsDAT0-DAT2, the terminals C10-C13 are data terminals DAT4-DAT7, theterminal C2 is a command terminal CMD, the terminal C5 is a clockterminal CLK, a terminal C4 is a power source terminal VCC, the terminalC3 is a ground terminal VSS, the terminal C6 is a second ground terminalVSS2, and the terminals C6A, C6B are the antenna terminals LA, LB. Thesecond ground terminal VSS2 is utilized for card insertion/extractiondetection in the memory card 41.

Exemplified in FIG. 12 is the array of the external interface terminalsof the memory card 41. The external interface terminals are formed intwo rows in a direction crossing the insertion direction A of the memorycard 41. The power source feeding terminals VSS, VCC are formed so as toextend over the two rows. The connector terminals of a card slot ascorrespond to the interface terminals of the first row lie frontward inthe card insertion direction A, with respect to the connector terminalsof the card slot as correspond to the interface terminals of the secondrow. In the case where the memory card originally includes the externalinterface terminal in the two rows, a time period till the cutoff of apower source can be easily made comparatively long by forming the powersource feeding terminals VCC, VSS so as to extend from the first rowover to the second row. Moreover, in the case where the memory card hasthe two terminal rows, the connector terminals of the card slot areoriginally in, at least, two rows, so that each of the power sourcefeeding terminals VSS, VCC can be easily brought into touch with thecorresponding connector terminal at two touch points, and the stabilityof power source feed can be easily coped with. In the examples of FIGS.11 and 12, any insertion/extraction detecting terminal is not providedas a dedicated terminal. Here, the second ground terminal VSS2 isutilized for the insertion/extraction detection. More specifically, thepower source terminal VCC and the second ground terminal VSS2 areconnected through a high resistance. In a state where the memory card 1is set in the card slot, the level of the second ground terminal VSS2lies at a ground potential. When the memory card 41 is extracted fromthe card slot, the second ground terminal VSS2 is held at a high leveluntil the power source terminal VCC has been separated from thecorresponding power source connector of the card socket. Thus, the cardcontroller 42 can recognize the extraction of the card 41. Upondetecting the extraction of the card 41, the card controller 42 executesan end process in the same manner as in the foregoing, before the cutoffof the power source.

Referring to FIG. 12, the antenna terminals LA, LB and the second groundterminal VSS2 are formed in regions obtained by dividing the region ofthe size of that interface terminal of the first row which isrepresented by the clock terminal CLK of the first row. The IC cardmicro computer 44 of the memory card 41 is of the noncontact interfacingtype as stated before. In this regard, in case of adopting the contactinterfacing type which interfaces with the exterior through the cardcontroller 42, the antenna terminals LA, LB and the second groundterminal VSS2 are replaced with a single second ground terminal VSS2.Accordingly, the terminal region of the size of the second groundterminal is utilized in such a memory card which is not adapted for thenoncontact interfacing, whereby the memory card 41 adapted for thenoncontact interfacing and including the two antenna connectionterminals LA, LB can be fabricated. A place where the two antennaconnection terminals LA, LB are formed, corresponds to the region wherethe second ground terminal is formed in the memory card which is notadapted for the noncontact interfacing and which does not have the datainput/output function based on the antenna. In a case where the memorycard 41 adapted for the noncontact interfacing has been inserted into acard slot for the memory card which is not adapted for the noncontactinterfacing, the antenna connection terminals LA, LB are connected to aground potential feeding connector terminal inside the card slot. Sincea ground potential does not have any AC component, namely, any signalcomponent, no problem is posed in the operation of the memory card 41.Even when a high-frequency component is superposed on the groundpotential by the antenna connection terminals LA, LB contrariwise, thispotential does not fluctuate greatly. Therefore, in the case where thememory card 41 in FIG. 11 has been inserted into the card slot for thememory card which is not adapted for the noncontact interfacing, anyinconvenience is not incurred by the connection of the signalingconnector terminal of the card slot side with the antenna connectionterminals LA, LB. On the other hand, in a case where the memory cardwhich is not adapted for the noncontact interfacing has been insertedinto the card slot for the noncontact interfacing type, the antennaconnecting connector terminals of the card slot is connected to thegrounding external terminal of the memory card which is not adapted forthe noncontact interfacing, and the antenna is short-circuited. However,an electromotive force based on the antenna is small, and the outputimpedance of the antenna is high, any inconvenience is not incurred bythe short-circuit of the antenna. As shown in FIG. 11, the antennaconnection terminals LA, LB are connected to the IC card microcomputer44 through capacitance elements Cac for AC coupling. Thus, a DCcomponent is reliably restrained from being superposed on the groundpotential from the antenna connection terminals LA, LB and through theground potential connector terminal of the card slot for the memory cardwhich is not adapted for the noncontact interfacing, and thetransmission of the signal component from the antenna is reliablyprevented from being hindered.

The arrangement of the external interface terminals of the memory card41 as shown in FIG. 13 differs from the arrangement in FIG. 12 in thepoint that the antenna terminals LA, LB are enlarged. The arrangement ofthe external interface terminals of the memory card 41 as shown in FIG.14 differs from the arrangement in FIG. 12 in the point that the frontand rear positions of the antenna terminals LA, LB and the second groundterminal VSS2 are reversed. The arrangement of the external interfaceterminals of the memory card 41 as shown in FIG. 15 differs from thearrangement in FIG. 13 in the point that the front and rear positions ofthe antenna terminals LA, LB and the second ground terminal VSS2 arereversed. The arrangement of the external interface terminals of thememory card 41 as shown in FIG. 16 differs from the arrangement in FIG.12 in the point that the second ground terminal VSS2 is abolished, andthat the antenna terminals LA, LB are lengthened correspondingly.

Although the invention made by the inventor has thus far been concretelydescribed in conjunction with the embodiments, it is needless to saythat the invention is not restricted to the foregoing embodiments, butthat it is variously alterable within a scope not departing from thepurport thereof.

By way of example, the definitions of the erase and the write may wellbe reverse to the foregoing ones. The stored information of eachnonvolatile memory cell is not restricted to two-valued data, but it maywell be four or more-valued data. The functions and designations of theexternal interface terminals of the memory card are appropriatelyalterable without being restricted to those described above. The memorycard may well include any data processor other than the IC cardmicrocomputer. The instruction of the end process for the flash memoryis not restricted to the case of using the reset signal, but any othersignal or command may well be used. The processing circuits of thememory card are not restricted to the interface control circuit and theflash memory. The flash memory is not restricted to one which isdedicated to the information storage, but it may well be one whichconstitutes a programmable logic array. Besides, the end process is notrestricted to a write-back process, a write completion process formanagement information, or the completion of a midway write operation,but it may well be any other process. Further, the decoupling capacitorsneed not always be disposed.

The invention is extensively applicable to semiconductor devices each ofwhich includes a nonvolatile memory capable of rewriting storedinformation and a control circuit therefor, and each of which is fedwith an operating power source from the exterior.

1. A semiconductor device which comprises external interface terminalsand processing circuits, and which is fed with an operating power sourcewhen detachably set in a host equipment, wherein: said externalinterface terminals include power source feeding terminals, anextraction detecting terminal, and other terminals; said power sourcefeeding terminals are long enough to keep touching correspondingterminals of the host equipment for, at least, a predetermined timeperiod since separation of said extraction detecting terminal from acorresponding terminal of the host equipment; said power source feedingterminals are formed to be longer in an extraction direction than saidextraction detecting terminal; said power source feeding terminals are apower source terminal and a ground terminal; and any power sourcecompensating capacitor is not connected between said power sourceterminal and said ground terminal.
 2. A semiconductor device accordingto claim 1, wherein decoupling capacitors are connected between saidpower source terminal and said ground terminal.
 3. A semiconductordevice according to claim 1, wherein said power source feeding terminalsare made longer than said extraction detecting terminal, also on a sideopposite to the extraction direction, and a length which said powersource feeding terminals protrude on the opposite side to the extractiondirection, beyond said extraction detecting terminal, is smaller than alength which they protrude in the extraction direction.
 4. Asemiconductor device which comprises external interface terminals andprocessing circuits, and which is fed with an operating power sourcewhen detachably set in a host equipment, wherein: said externalinterface terminals include power source feeding terminals, anextraction detecting terminal, and other terminals; said power sourcefeeding terminals are long enough to touch corresponding terminals ofthe host equipment for, at least, 1.0 millisecond since separation ofsaid extraction detecting terminal from a corresponding terminal of thehost equipment, with respect to an extraction speed of 2.5meters/second; said power source feeding terminals are a power sourceterminal and a ground terminal; and any power source compensatingcapacitor is not connected between said power source terminal and saidground terminal.
 5. A semiconductor device according to claim 4, whereindecoupling capacitors are connected between said power source terminaland said ground terminal.
 6. A semiconductor device according to claim5, wherein said power source feeding terminals are formed to be longerin an extraction direction than said extraction detecting terminal.
 7. Asemiconductor device according to claim 6, wherein said power sourcefeeding terminals are made longer than said extraction detectingterminal, also on a side opposite to the extraction direction, and alength which said power source feeding terminals protrude on theopposite side to the extraction direction, beyond said extractiondetecting terminal, is smaller than a length which they protrude in theextraction direction.
 8. A semiconductor device which comprises externalinterface terminals and processing circuits, and which is fed with anoperating power source when detachably set in a host equipment, wherein:said external interface terminals are arranged in two rows in adirection crossing an extraction direction, and they include powersource feeding terminals, an extraction detecting terminal, and otherterminals; said power source feeding terminals are long so as to extendfrom the first row over to the second row; said power source feedingterminals are a power source terminal and a ground terminal; and anypower source compensating capacitor is not connected between said powersource terminal and said ground terminal.
 9. A semiconductor deviceaccording to claim 8, wherein decoupling capacitors are connectedbetween said power source terminal and said ground terminal.